DocumentCode
2834967
Title
Re-evaluation mode timing simulation
Author
Chew, Marko ; Strojwas, Andrzej J.
Author_Institution
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear
1991
fDate
11-14 Jun 1991
Firstpage
2395
Abstract
The authors describe a computationally inexpensive technique for evaluating different process conditions on a circuit´s timing response. Due to manufacturing variations, the propagation of signals through a given path in a circuit is characterized by a statistical distribution. The Monte Carlo method requires the execution of multiple simulation runs of the same input pattern with different process conditions. The authors developed a technique called reevaluation mode simulation which can handle a wider range of process conditions since logic behavior is considered. Techniques for inexpensively evaluating the effects of different process conditions on circuit path delays have not considered the logic behavior. Consequently, the range of process conditions accommodated by these techniques is unnecessarily limited. It is this accounting for logic behavior that distinguishes this technique from the earlier work. The execution speed advantage of the technique over that of a conventional simulation stems from utilizing the information generated by the conventional simulation step
Keywords
delays; digital simulation; circuit path delays; execution speed; logic behavior; manufacturing variations; mode timing simulation; multiple simulation; process conditions; reevaluation mode simulation; signal propagation; statistical distribution; timing response; Circuit simulation; Circuit testing; Computational modeling; Computer aided manufacturing; Delay; Discrete event simulation; Logic devices; Statistical distributions; Timing; Virtual manufacturing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN
0-7803-0050-5
Type
conf
DOI
10.1109/ISCAS.1991.176861
Filename
176861
Link To Document