Title :
Fast timing analysis of VLSI circuits: a dynamic and hierarchical approach
Author :
Blaquière, Yves ; Dagenais, Michel ; Savaria, Yvon
Author_Institution :
Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada
Abstract :
A new and efficient procedure is proposed to evaluate the timing performance of VLSI circuits with circuit-level accuracy. The efficiency is obtained by dynamically changing the circuit hierarchy level and the delay model during the analysis. The analysis is performed at high level to rapidly identify the critical portions of the circuit. These critical portions are then successively studied at a more detailed level for maximal accuracy. This new procedure, which was implemented and applied to several large circuits, is shown to significantly reduce the analysis time
Keywords :
VLSI; circuit analysis computing; delays; VLSI circuits; circuit hierarchy level; circuit-level accuracy; delay model; timing analysis; timing performance; Circuit analysis; Circuit simulation; Computational modeling; Design automation; Logic; Monte Carlo methods; Performance analysis; Propagation delay; Timing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN :
0-7803-0050-5
DOI :
10.1109/ISCAS.1991.176862
