Title :
On-chip measurements of standard-cell propagation delay
Author :
Churayev, S.O. ; Matkarimov, B.T. ; Paltashev, T.T.
Author_Institution :
Kazakh-British Tech. Univ., Almaty, Kazakhstan
Abstract :
We report on implementation of random sampling methodology for on-chip measurements of the pin-to-pin propagation delay of single standard cells of core library. A test chip has been implemented in 0.13 μm GL130SB (130 nm Logic Process) technology at Dongbu HiTek and used to monitor up to picosecond´s timing behavior of 32 DUT´s of core library. Observed mismatch between simulated and measured parameters helps to improve and verify library cell models.
Keywords :
delay circuits; logic circuits; logic testing; DUT; core library; library cell models; logic process technology; on-chip measurements; pin-to-pin propagation delay; random sampling methodology; size 0.13 mum; standard-cell propagation delay; test chip; Delay; Generators; Libraries; Propagation delay; Radiation detectors; Synchronization; System-on-a-chip;
Conference_Titel :
Design & Test Symposium (EWDTS), 2010 East-West
Conference_Location :
St. Petersburg
Print_ISBN :
978-1-4244-9555-9
DOI :
10.1109/EWDTS.2010.5742113
