Title :
Path delay faults and ENF
Author :
Matrosova, A. ; Lipsky, V. ; Melnikov, A. ; Singh, Virendra
Author_Institution :
Tomsk State Univ., Tomsk, Russia
Abstract :
Single path delay faults (PDFs) are considered. They are reduced to temporal faults of ENF literals. These temporal faults exist during delay time of the relevant paths and then disappear. Deriving test pair v1, v2 for robust and non-robust PDFs is based on analyses of products of free fault and fault ENF. Some properties of these test pairs are determined. Possibilities of using these properties to cut the length of the test detecting all PDFs of a combinational circuit are shown.
Keywords :
combinational circuits; logic testing; ENF; PDF; combinational circuit; delay time; equivalent normal form; single-path delay faults; temporal faults; test pair; Circuit faults; Combinational circuits; Delay; Indexes; Integrated circuit modeling; Logic gates; Robustness;
Conference_Titel :
Design & Test Symposium (EWDTS), 2010 East-West
Conference_Location :
St. Petersburg
Print_ISBN :
978-1-4244-9555-9
DOI :
10.1109/EWDTS.2010.5742130