DocumentCode
2835876
Title
The Metaflow Lightning chipset
Author
Lightner, B.D. ; Hill, G.
Author_Institution
Metaflow Technol. Inc., San Diego, CA, USA
fYear
1991
fDate
Feb. 25 1991-March 1 1991
Firstpage
13
Lastpage
18
Abstract
The Lightning SPARC superscalar microprocessor chipset is the first processor to implement the Metaflow architecture. This architecture exploits instruction-level parallelism present in conventional sequential programs by hardware means, without relying on sophisticated optimizing compilers. The Lightning processor is capable of executing instructions out of order and speculatively. Lighting is based on an integrated instruction-shelving structure called the DRIS (deferred-scheduling, register-renaming instruction shelf). All instructions are placed in the DRIS as they are fetched. A dataflow based instruction scheduler selects instructions for execution from the DRIS after all needed operands have been computed. Instruction results are shelved in the DRIS along with instructions. Instructions are removed from the DRIS, and their results are written to permanent storage, in the order in which they were fetched. Instructions following conditional branches are executed speculatively, based on a predicted direction; the effects of a mispredicted branch are quickly repaired.<>
Keywords
instruction sets; microprocessor chips; DRIS; Metaflow Lightning chipset; SPARC superscalar microprocessor; dataflow based instruction scheduler; deferred-scheduling; instruction-level parallelism; integrated instruction-shelving structure; register-renaming instruction shelf; Clocks; Job shop scheduling; Large scale integration; Lightning; Logic; Microprocessors; Out of order; Processor scheduling; Program processors; Trademarks;
fLanguage
English
Publisher
ieee
Conference_Titel
Compcon Spring '91. Digest of Papers
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-8186-2134-6
Type
conf
DOI
10.1109/CMPCON.1991.128776
Filename
128776
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