A multiprocessor architecture with memory-coupled multilevel hierarchical bus structure

The design aspects of the topology of the architecture based on specifications are discussed. The simulation modeling of the proposed architecture is described. It is based on uniformly distributed random numbers representing the probability of a request from a processor for local memory or a shared memory at a higher level bus in the multilevel architecture. The results of the simulation are presented, and the performance of a single time-shared bus structure is compared with a multilevel hierarchical bus structure. The multi level hierarchical structure is found to offer better performance