Cosimulation Tool for FPGA-based Algorithm Validation

This paper introduces a cosimulation tool that enables the validation of FPGA algorithms by simulating them with Saber simulation package. The algorithm encoded with Quartus II Web Edition by Altera is compiled to create a compatible VHDL file. The latter is imported into a Saber schematic and simulated in the electrical environment. A digital sliding mode observer dedicated to the flying capacitor voltage estimation of a stacked multicell converter (SMC) is taken as an example to demonstrate and validate the developed technique. The latter also ensures the correctness of the VHDL file to be downloaded into the FPGA of the physical system. After a short reminder on the SMC topology, this article summarizes briefly the sliding mode observer design for the intermediate voltages of the structure as well as its digitizing. It then details the cosimulation technique and compares the co-simulated estimates with the first experimental results. The last part presents the conclusion and perspectives of this study.