Systematic steps in design of a CMOS two-stage cascode-compensated OTA

Cascode compensation increases the speed of two stage amplifiers compared to conventional Miller compensation. The cost is an increase of pole zero complexity such that traditional open loop analysis will not lead to intuitive design equations. This paper introduces a systematic design approach of cascode compensated two stage OTAs. The parametric transfer function, settling error and thermal noise equations were first extracted from the small signal equivalent circuit of the OTA, then a set of poles and zeros which best suited settling requirements was asserted into the non-linear equations relating pole zero and circuit parameters, through which circuit parameters were calculated. Using the system level results Spice simulation of the OTA was performed in a 0.35 μm CMOS process. The simulated OTA achieved a DC-gain of 100dB with a 120MHz bandwidth and a 62° phase margin from a 3V power supply. The measured dissipated power was 2.01 mW with a settling time of 7 nSec.