VLSI implementation of adaptors using systolic arrays

The use of systolic and wavefront arrays to increase throughput in digital signal processors has been increasing over recent years. A bit-level systolic structure is developed which realises the basic building block of two important classes of wave digital filters, the 2-port adaptor. This structure is fully pipelined and is thus capable of use in high sampling rate applications. A Hilo model is described which has been used in design verification. The VLSI design of a prototype adaptor using ES2´s 2 μm double metal CMOS process is also presented together with the results from a circuit simulation. Details of the number of transistors, chip area, power dissipation, etc., both for the prototype design and more realistic designs are included