Title :
A 2-rail logic combinational circuit with easy detection of stuck-open and stuck-on faults in FETs
Author_Institution :
Dept. of Inf. & Comput. Sci., Chiba Univ., Japan
Abstract :
A design method for a 2-rail logic combinational circuit is proposed, where stuck-open and stuck-on faults in FETs can be easily detected. In the proposed circuit design, 4 FETs are added to each gate in a conventional 2-rail logic circuit. Two logical gates, OR and AND, are also added to the circuit as fault observing gates. A test can be easily generated and fault observation is easy. Stuck-at faults and stuck-open faults on lines are also detected by the test
Keywords :
CMOS integrated circuits; built-in self test; combinatorial circuits; design for testability; fault location; integrated logic circuits; logic testing; 2-rail logic circuit; 2-rail logic combinational circuit; CMOS; DFT; FETs; logical gates; self test; stuck-on faults; stuck-open; Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Design methodology; Electrical fault detection; FETs; Fault detection; Logic circuits; Logic design;
Conference_Titel :
Fault Tolerant Systems, 1991. Proceedings., Pacific Rim International Symposium on
Conference_Location :
Kawasaki
Print_ISBN :
0-8186-2275-X
DOI :
10.1109/{RFTS.1991.212937
