Test generation algorithm for incomplete scan design circuits with tri-state devices

The paper describes a heuristic algorithm, DALG-EX18, for generating test patterns of incomplete scan design circuits with tri-state devices. The algorithm is based on the philosophy of the extended D-algorithm. Logic circuits consisting of gates, flip-flops and functional modules can be treated. Testability measures are utilized to accelerate D-drive and reduce the number of conflicts in the consistency. In the algorithm, the problems of memory retention and bus clash in circuits with tri-state devices can be solved, clock lines in an incomplete scan design circuit can be considered. AC program of the algorithm is implemented on a VAX 11/750 and results for some circuits are shown