Test generation algorithm for incomplete scan design circuits with tri-state devices

Author

Shi, Zhi-gang ; Lin, Zheng-Hui

Author_Institution

VLSI Res. Inst. Shanghai Jiao Tong Univ., China

fYear

1991

fDate

26-27 Sep 1991

Firstpage

206

Lastpage

211

Abstract

The paper describes a heuristic algorithm, DALG-EX18, for generating test patterns of incomplete scan design circuits with tri-state devices. The algorithm is based on the philosophy of the extended D-algorithm. Logic circuits consisting of gates, flip-flops and functional modules can be treated. Testability measures are utilized to accelerate D-drive and reduce the number of conflicts in the consistency. In the algorithm, the problems of memory retention and bus clash in circuits with tri-state devices can be solved, clock lines in an incomplete scan design circuit can be considered. AC program of the algorithm is implemented on a VAX 11/750 and results for some circuits are shown

Keywords

automatic testing; heuristic programming; logic testing; ternary logic; DALG-EX18; VAX 11/750; bus clash; extended D-algorithm; flip-flops; functional modules; gates; heuristic algorithm; incomplete scan design circuits; memory retention; test patterns; tri-state devices; Algorithm design and analysis; Circuit faults; Circuit testing; Clocks; Design methodology; Flip-flops; Logic circuits; Logic testing; Sequential analysis; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Fault Tolerant Systems, 1991. Proceedings., Pacific Rim International Symposium on

Conference_Location

Kawasaki

Print_ISBN

0-8186-2275-X

Type

conf

DOI

10.1109/{RFTS.1991.212944

Filename

212944