A 25 Gb/s 5.8 mW CMOS Equalizer

Author

Jun Won Jung ; Razavi, Behzad

Author_Institution

Electr. Eng. Dept., Univ. of California, Los Angeles, Los Angeles, CA, USA

Volume

50

Issue

2

fYear

2015

fDate

Feb. 2015

Firstpage

515

Lastpage

526

Abstract

Low-power equalization remains in high demand for wireline receivers operating at tens of gigabits per second in copper media. This paper presents a design incorporating a continuous-time linear equalizer and a two-tap half-rate/quarter-rate decision-feedback equalizer that exploits charge steering techniques to reduce the power consumption. Realized in 45 nm technology, the prototype draws 5.8 mW from a 1 V supply and compensates for 24 dB of loss with BER <;10^-12.

Keywords

CMOS integrated circuits; copper; decision feedback equalisers; error statistics; low-power electronics; radio receivers; BER; CMOS equalizer; Cu; bit rate 25 Gbit/s; charge steering; continuous-time linear equalizer; copper media; loss 24 dB; low-power equalization; power 5.8 mW; quarter-rate decision feedback equalizer; size 45 nm; two-tap half-rate; voltage 1 V; wireline receivers; Clocks; Decision feedback equalizers; Latches; Optical signal processing; Power demand; Topology; Charge steering; decision feedback; equalizer; linear equalizer; nonlinearity;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2014.2364271

Filename

6948275