An efficient power reduction technique for low power data I/O for military applications

In many digital processors which are mostly used in avionics, power dissipation in the processor plays a major role. Several encoding techniques have been proposed to reduce the power dissipation. In digital circuits most of the power is dissipated as dynamic power for charging and discharging of node capacitance. A majority of power reduction methods attempt to reduce the number of effective bus transitions. But, de facto in Deep Submicron (DSM) technology the distance between the two adjacent wires is very small and the effect of inter-wire (coupling) capacitances will dominate substrate (base) capacitances. So, in the presence of coupling effects, the previous techniques of power reduction in digital processors which are mainly based on self transitions may not achieve the goal. This paper proposes a new data bus encoding scheme, in which coupling transitions of bus lines along with self transitions are considered. Simulation results show that proposed encoding scheme reduces effective transitions related to power dissipation (considering the power due to Codec), by as much as 18% for 8, 16, 32-bit bus, indicating that the proposed coding scheme is suitable for low power design.