DocumentCode
2839148
Title
A light-weight statically scheduled network-on-chip
Author
Sorensen, R.B. ; Schoeberl, Martin ; Sparso, J.
Author_Institution
Dept. of Inf. & Math. Modeling, Tech. Univ. of Denmark, Lyngby, Denmark
fYear
2012
fDate
12-13 Nov. 2012
Firstpage
1
Lastpage
6
Abstract
This paper investigates how a light-weight, statically scheduled network-on-chip (NoC) for real-time systems can be designed and implemented. The NoC provides communication channels between all cores with equal bandwidth and latency. The design is FPGA-friendly and consumes a minimum of resources. We implemented a 64 core 16-bit multiprocessor connected with the proposed NoC in a low-cost FPGA.
Keywords
field programmable gate arrays; integrated circuit design; logic design; microprocessor chips; network-on-chip; FPGA; communication channels; multiprocessor; network-on-chip; real-time systems; word length 16 bit; Clocks; Field programmable gate arrays; Program processors; Random access memory; Registers; Schedules; Time division multiplexing;
fLanguage
English
Publisher
ieee
Conference_Titel
NORCHIP, 2012
Conference_Location
Cpenhagen
Print_ISBN
978-1-4673-2221-8
Electronic_ISBN
978-1-4673-2222-5
Type
conf
DOI
10.1109/NORCHP.2012.6403129
Filename
6403129
Link To Document