Title :
An accurate fault location method based on configuration bitstream analysis
Author :
Zhou Jing ; Liu Zengrong ; Chen Lei ; Wang Shuo ; Wen Zhiping ; Chen Xun ; Qi Chang
Author_Institution :
FPGA Dept., Beijing Microelectron. Technol. Instn., Beijing, China
Abstract :
As SRAM-based FPGAs are increasingly being used; there are more and more researches on the SEU effects of FPGA. To emulate the effects of SEUs, a variety of fault injection techniques have been studied. As fault injection process is black box testing method, it helps little to SEU mechanism study. For further study of the SEU effects and the mitigation techniques, a novel accurate fault location method is studied in this paper. The Accurate Fault Location System (AFLS) based on this method is developed to locate faults, which are detected by the fault injection system, in the FPGA resources. The precise location of resource corresponding to the faults will be obtained by converting the configuration bit location into FPGA resource physical location. Using this system will help the study of SEU effects and the mitigation techniques, and then encourage the utilization of FPGAs for space-based applications.
Keywords :
SRAM chips; fault diagnosis; field programmable gate arrays; integrated circuit testing; logic testing; AFLS; FPGA resource physical location; SEU effect; SEU mechanism; SRAM-based FPGA; accurate fault location system; black box testing; configuration bit location; configuration bitstream analysis; fault detection; fault injection system; mitigation technique; space-based application; Circuit faults; Fault location; Field programmable gate arrays; Indexes; Single event upset; System-on-a-chip; Table lookup; FPGA; SEU; configuration bitstream decode; fault locating;
Conference_Titel :
NORCHIP, 2012
Conference_Location :
Cpenhagen
Print_ISBN :
978-1-4673-2221-8
Electronic_ISBN :
978-1-4673-2222-5
DOI :
10.1109/NORCHP.2012.6403144
