Packaging of Cu/low-k IC devices: a novel surface passivation and direct fine-pitched gold wirebond ball interconnects analysis

The trend towards finer pitch and higher performance devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. Compared to the commonly used aluminum metallization scheme on the traditional silicon dioxide and/or silicon nitride passivation, a Cu/low-k combination offers higher on-chip communication speed and a lower overall device cost. But the process of packaging Cu/low-k devices has been proven to be difficult, relying either on additional lithography and deposition steps or on costly new process tools. Thus, this work presents a novel methodology to bond fine pitch Au wire directly onto the Cu/low-k pad structure using the industry standard tool set. A Cu/low-k test vehicle is designed with the required slotted low-k fillings for dual damascene CMP process need. In addition, a thin organic passivation film is developed for coating the exposed Cu/low-k pad temporarily from copper oxidation and to provide a wirebondable surface to form the proper interconnects. A design of experiment is performed to optimize wirebonding parameters (power, time, and USG bleed), along with key physical contributors from wafer sawing and die attaching steps that impact the interconnect shear strength and quality. In addition, electrical and optical characterization and surface failure analysis are performed to confirm the feasibility of the technology. Finally, reliability results of the pad structure design and recommendations for further process optimization are presented.