Title :
Dynamic circuit techniques using independently controlled double-gate devices
Author :
Kuang, J.B. ; Kim, K. ; Chuang, C.T. ; Ngo, H.C. ; Nowka, K.J.
Author_Institution :
Austin Res. Lab., IBM Res. Div., USA
Abstract :
In this paper, conditional keeper, charge sharing prevention, and clock load reduction techniques for symmetrical and asymmetrical DG devices have been presented. Performance benefit, noise immunity, area and power efficiency can be achieved when technology features are judiciously utilized in the design of dynamic circuits.
Keywords :
field effect transistors; logic design; logic gates; asymmetrical double-gate devices; charge sharing prevention technique; clock load reduction technique; conditional keeper technique; dynamic circuit techniques; symmetrical double-gate devices; Capacitance; Circuit noise; Circuit synthesis; Degradation; Delay effects; Employment; Laboratories; Logic devices; Logic gates; Robustness;
Conference_Titel :
SOI Conference, 2005. Proceedings. 2005 IEEE International
Print_ISBN :
0-7803-9212-4
DOI :
10.1109/SOI.2005.1563539
