• DocumentCode
    2839945
  • Title

    Independent gate skewed logic in double-gate SOI technology

  • Author

    Cakici, Tamer ; Mahmoodi, Hamid ; Mukhopadhyay, Saibal ; Roy, Kaushik

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
  • fYear
    2005
  • fDate
    3-6 Oct. 2005
  • Firstpage
    83
  • Lastpage
    84
  • Abstract
    Independent gate control of double gate SOI devices (D. Fried, 2003 and L. Mathew, 2004) can be effectively exploited to improve performance and reduce power in sub-50nm circuits. In this paper, we have proposed a skewed logic style using independent gate operation of double gate SOI devices.
  • Keywords
    logic gates; silicon-on-insulator; double gate SOI devices; double-gate SOI technology; independent gate control; skewed logic; Circuit simulation; Delay; Design engineering; Inverters; Logic devices; Logic gates; MOS devices; MOSFETs; Power engineering and energy; Power engineering computing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, 2005. Proceedings. 2005 IEEE International
  • ISSN
    1078-621X
  • Print_ISBN
    0-7803-9212-4
  • Type

    conf

  • DOI
    10.1109/SOI.2005.1563543
  • Filename
    1563543
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2839945