Title :
High-density logic techniques with reduced-stack double-gate MOSFETs
Author :
Chiang, Meng-Hsueh ; Kim, Keunwoo ; Chuang, Ching-Te ; Tretz, Christophe
Author_Institution :
National Ilan Univ., Taiwan
Abstract :
We have presented a high-density DG logic circuit technique exploiting the unique VT modulation effect through the extended gate-to-gate coupling in high-VT symmetrical DG devices. The scheme reduces the number of stacked transistors (hence area/capacitance and standby/dynamic power), and improves performance. The performance improvement and power reduction are evaluated/validated using mixed-mode two-dimensional numerical simulations.
Keywords :
MOSFET; integrated circuit design; logic design; logic gates; 2D numerical simulations; DG logic circuit technique; double-gate MOSFET; gate-to-gate coupling; high-density logic techniques; modulation effect; symmetrical DG devices; CMOS technology; Design engineering; Logic circuits; Logic design; Logic devices; Logic functions; Logic gates; MOSFETs; Numerical simulation; Performance analysis;
Conference_Titel :
SOI Conference, 2005. Proceedings. 2005 IEEE International
Print_ISBN :
0-7803-9212-4
DOI :
10.1109/SOI.2005.1563544
