Title :
Research and Implementation of Test Pattern Generation Based on General structure Model of SOC
Author :
Gu Jing ; Zhichao Wang ; Xiaoyang Yu
Author_Institution :
Inst. of Comput. Sci. & Technol., Harbin Univ. of Sci. & Technol., Harbin, China
Abstract :
The test vector generation algorithm and the compression algorithm based on general structure model of SoC was introduced in this paper. We have analyzed the PODEM algorithm for test vectors generation and translated the test pattern, and then formed the SoC general structural model test vector. Through the experimental comparison, we find the use of Golomb coding for test vector compression/decompression method is simple and effective, and test data compression rate improved by using the minimizing Hamming distance sorting algorithm to compress and decompress the test vector significantly.
Keywords :
automatic test pattern generation; data compression; sorting; system-on-chip; Golomb coding; Hamming distance sorting algorithm; PODEM algorithm; SoC general structural model test vector; system-on-chip; test pattern generation; test vector compression method; test vector decompression method; test vector generation algorithm; Application specific integrated circuits; Automatic test pattern generation; Circuit faults; Circuit testing; Computer science; Hamming distance; Integrated circuit technology; Intellectual property; Semiconductor process modeling; Test pattern generators;
Conference_Titel :
Information Engineering and Computer Science, 2009. ICIECS 2009. International Conference on
Conference_Location :
Wuhan
Print_ISBN :
978-1-4244-4994-1
DOI :
10.1109/ICIECS.2009.5364701
