DocumentCode
2840014
Title
MediaMem: A dynamically adjustable memory subsystem for high-bandwidth required multimedia SoC systems
Author
Chu, Slo-Li ; Lo, Min-Jen ; Yang, Hsiao-Wen
Author_Institution
Dept. of Inf. & Comput. Eng., Chung Yuan Christian Univ., Chungli
fYear
2008
fDate
4-6 Aug. 2008
Firstpage
1
Lastpage
8
Abstract
Since the continuously growing of multimedia functionalities in modern portable consuming electronics, the computer systems have to integrate multiple media processors on single chip/system to provide better service. However, the insufficient bandwidth of the memory subsystem will make the performance of the multimedia modules unsatisfied. In this paper, we propose an innovative architecture of memory subsystem, aiming for extracting more potential bandwidth of memory access to fulfill the requirements of multiple multimedia processors dynamically. The proposed architecture, called MediaMem, can offers satisfied bandwidth for all attached multimedia processor by proposed two novel scheduling mechanisms that can dynamically adjust the access grants, buffer sizes, and transfer sequences according to real-time situations. Additionally, the memory interconnection is modified to avoid bus contention. The proposed MediaMem architecture has been implemented by SystemC HDL. The whole system functional verification and performance evaluation have been exam by CoWare ConvergenSC. The experimental results are also discussed.
Keywords
buffer storage; memory architecture; multimedia computing; processor scheduling; system-on-chip; CoWare ConvergenSC; MediaMem architecture; SystemC HDL; access grant; buffer size; computer systems; dynamically adjustable memory subsystem; high-bandwidth required multimedia SoC system; media processors; memory access; memory interconnection; memory subsystem architecture; multimedia functionality; multimedia modules; portable consuming electronics; scheduling mechanism; transfer sequence; Bandwidth; Dynamic scheduling; Hardware design languages; Multimedia systems; Portable computers; Processor scheduling; Random access memory; Read-write memory; Streaming media; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Systems Architecture Conference, 2008. ACSAC 2008. 13th Asia-Pacific
Conference_Location
Hsinchu
Print_ISBN
978-1-4244-2682-9
Electronic_ISBN
978-1-4244-2683-6
Type
conf
DOI
10.1109/APCSAC.2008.4625450
Filename
4625450
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