Planar double gate transistors with asymmetric independent gates

Author

Ilicali, G. ; Weber, W. ; Rösner, W. ; Dreeskornfeld, L. ; Hartwich, J. ; Kretz, J. ; Lutz, Tarek ; Mazellier, J.-P. ; Städele, Martin ; Specht, Michael ; Luyken, J.R. ; Landgraf, E. ; Hofmann, F. ; Risch, L. ; Käsmaier, R. ; Hansch, W.

Author_Institution

Infineon Technol. AG, Munich, Germany

fYear

2005

fDate

3-6 Oct. 2005

Firstpage

126

Lastpage

127

Abstract

Planar double-gate field effect transistors with asymmetric (p++/n++) independent gates down to 55nm physical gate lengths are successfully fabricated. A fabrication concept, epi-before-bonding, is introduced and demonstrated to be highly successful in achieving ultra-thin and planar Si bodies. Various modes of operations are extensively analyzed and compared to 2D simulations. It is experimentally shown that specific off-current requirements can be fulfilled with conventional poly-Si gates.

Keywords

field effect transistors; nanotechnology; semiconductor device manufacture; 2D simulations; 55 nm; asymmetric independent gates; epi-before-bonding fabrication concept; off-current requirements; planar Si bodies; planar double-gate field effect transistors; ultra-thin bodies; Analytical models; Capacitive sensors; Degradation; Double-gate FETs; Etching; Fabrication; Lithography; Oxidation; Silicon; Thickness control;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2005. Proceedings. 2005 IEEE International

ISSN

1078-621X

Print_ISBN

0-7803-9212-4

Type

conf

DOI

10.1109/SOI.2005.1563562

Filename

1563562