A novel technique to calculate the critical temperature of thermal agglomerations on patterned SOI wafers

Thermal agglomeration of ultra-thin SOI (<20nm) is an undesirable issue for device fabrication. In this article for the first time, a methodology to calculate the critical temperature and agglomeration rate on patterned SOI wafers with different thicknesses, ranging from 5.9nm to 12.1nm has been established. This study also presents the agglomeration effect on patterned SOI wafers for silicon structure shape, undoped, n-type doped, and p-type doped. The developed method has been tested and compared in context of previous papers published on non-patterned films presented in Y. Ishikawa et al. (2002). In addition, detailed analysis on various surface morphologies at different temperatures has been included.