Title :
Fin thickness asymmetry effects in multiple-gate SOI FETs (MuGFETs)
Author :
Schulz, T. ; Xiong, W. ; Cleavelin, C.R. ; Schruefer, K. ; Gostkowski, M. ; Matthews, K. ; Gebara, G. ; Zaman, R.J. ; Patruno, P. ; Chaudhry, A. ; Woo, A. ; Colinge, J.P.
Author_Institution :
Infineon Technol., Austin, TX, USA
Abstract :
Fin thickness non-uniformity is a potential shortcoming of vertical multiple-gate devices such as FinFETs and tri-gate FETs. In this paper a test structure with intentionally misaligned gates is used to investigate the sensitivity of electrical characteristics on fin thickness variations.
Keywords :
MOSFET; silicon-on-insulator; FinFET; electrical characteristics; fin thickness; multiple gate SOI FET; tri-gate FET; vertical multiple gate devices; Degradation; Electrodes; FETs; FinFETs; Ion implantation; Lithography; MOS devices; MOSFETs; Silicon; Threshold voltage;
Conference_Titel :
SOI Conference, 2005. Proceedings. 2005 IEEE International
Print_ISBN :
0-7803-9212-4
DOI :
10.1109/SOI.2005.1563571
