Title :
CMOS PA-RISC processor for a new family of workstations
Author :
Forsyth, M. ; Mangelsdorf, S. ; Delano, E. ; Gleason, C. ; Yetter, J. ; Steiss, D.
Author_Institution :
Hewlett Packard Co., Fort Collins, CO, USA
fDate :
Feb. 25 1991-March 1 1991
Abstract :
A novel low-cost, high-performance RISC (reduced instruction set computer) processor chip set implementing Hewlett Packard´s PA-RISC instruction set has been developed. The design consists of a CPU chip containing 577 K transistors implemented in HP´s CMOS26 technology and a floating-point coprocessor containing 640 K transistors and implemented in Texas Instruments´ EPIC-2 CMOS technology. Key features of the design include a 66 MHz clock frequency, large configurable cache memories utilizing industry standard SRAMs, and several implementation features designed to improve floating-point and graphics performance.<>
Keywords :
CMOS integrated circuits; microprocessor chips; reduced instruction set computing; 66 MHz; CMOS26 technology; CPU chip; EPIC-2 CMOS technology; Hewlett Packard; PA-RISC instruction set; SRAMs; Texas Instruments; configurable cache memories; floating-point coprocessor; graphics performance; reduced instruction set computer; CMOS process; CMOS technology; Cache memory; Clocks; Computer aided instruction; Coprocessors; Frequency; Instruments; Reduced instruction set computing; Workstations;
Conference_Titel :
Compcon Spring '91. Digest of Papers
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-2134-6
DOI :
10.1109/CMPCON.1991.128807
