Title :
Back-gate controlled READ SRAM with improved stability
Author :
Kim, Jae-Joon ; Kim, Keunwoo ; Chuang, Ching-Te
Author_Institution :
IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
We have presented a novel back-gate controlled UTSOI SRAM cell structure and associated design considerations. The proposed scheme offers improved stability compared with conventional 6T cell, and has less number of transistors than the conventional 10T cell. Due to over 3× improvement in SNM even at low VDD and reduced area penalty compared with 10T cell, the proposed 8T cell could be aggressively scaled down. This scheme can also be applied to SRAM cells with asymmetrical DG devices.
Keywords :
SRAM chips; memory architecture; silicon-on-insulator; READ SRAM; SRAM cell structure; UTSOI; asymmetrical DG devices; back-gate control; ultra-thin silicon-on-insulator; Back; Degradation; Fluctuations; Logic; Random access memory; Silicon; Stability; Threshold voltage; Transistors; Very large scale integration;
Conference_Titel :
SOI Conference, 2005. Proceedings. 2005 IEEE International
Print_ISBN :
0-7803-9212-4
DOI :
10.1109/SOI.2005.1563591