Author :
Vandooren, A. ; Hobbs, C. ; Faynot, O. ; Perreau, P. ; Denorme, S. ; Fenouillet-Beranger, C. ; Gallon, C. ; Morin, C. ; Zauner, A. ; lmbert, G. ; Bernard, H. ; Garnier, P. ; Gabette, L. ; Broekaart, M. ; Aminpur, M. ; Barnola, S. ; Loubet, N. ; Dutartre,
Abstract :
A low power 45nm fully-depleted SOI technology is demonstrated for the first time on 300mm SOI wafers, using direct metal gate on high k dielectric and selective silicon epitaxy. Short p-channel devices exhibit very good performance. SRAM bit cells are fully functional down to 0.525μm2 with good SNM and low leakage.
Keywords :
CMOS integrated circuits; SRAM chips; dielectric materials; silicon; silicon-on-insulator; 300 mm; 45 nm; SOI CMOS technology; SOI wafers; SRAM bit cell; Si; direct metal gate; elevated source/drain; fully-depleted SOI technology; high k dielectric; selective silicon epitaxy; short p-channel devices; CMOS technology; Fabrication; Hafnium; High K dielectric materials; High-K gate dielectrics; Integrated circuit technology; Intrusion detection; Silicon; Threshold voltage; Tin;
