DocumentCode
2840743
Title
0.525μm2 6T-SRAM bit cell using 45nm fully-depleted SOI CMOS technology with metal gate, high k dielectric and elevated source/drain on 300mm wafers
Author
Vandooren, A. ; Hobbs, C. ; Faynot, O. ; Perreau, P. ; Denorme, S. ; Fenouillet-Beranger, C. ; Gallon, C. ; Morin, C. ; Zauner, A. ; lmbert, G. ; Bernard, H. ; Garnier, P. ; Gabette, L. ; Broekaart, M. ; Aminpur, M. ; Barnola, S. ; Loubet, N. ; Dutartre,
Author_Institution
Freescale Semicond., Crolles, France
fYear
2005
fDate
3-6 Oct. 2005
Firstpage
221
Lastpage
222
Abstract
A low power 45nm fully-depleted SOI technology is demonstrated for the first time on 300mm SOI wafers, using direct metal gate on high k dielectric and selective silicon epitaxy. Short p-channel devices exhibit very good performance. SRAM bit cells are fully functional down to 0.525μm2 with good SNM and low leakage.
Keywords
CMOS integrated circuits; SRAM chips; dielectric materials; silicon; silicon-on-insulator; 300 mm; 45 nm; SOI CMOS technology; SOI wafers; SRAM bit cell; Si; direct metal gate; elevated source/drain; fully-depleted SOI technology; high k dielectric; selective silicon epitaxy; short p-channel devices; CMOS technology; Fabrication; Hafnium; High K dielectric materials; High-K gate dielectrics; Integrated circuit technology; Intrusion detection; Silicon; Threshold voltage; Tin;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 2005. Proceedings. 2005 IEEE International
ISSN
1078-621X
Print_ISBN
0-7803-9212-4
Type
conf
DOI
10.1109/SOI.2005.1563595
Filename
1563595
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