Title :
Xilinx Virtex II Pro implementation of a reconfigurable UMTS digital channel filter
Author :
Chandran, J. ; Kaluri, R. ; Singh, J. ; Owall, V. ; Veljanovski, R.
Abstract :
A reconfigurable digital root raised cosine (RRC) filter for a UMTS terrestrial radio access (UTRA) mobile terminal receiver is implemented on a Xilinx Vitrex II Pro Field Programmable Gate Array (FPGA). The filter employs a finite impulse response (FIR) and monitors in-band and out-of-band received signal powers and calculates the appropriate filter length that meets the bit-energy to interference ratio (Eb/No) of the system. The results presented are for the time division duplex (TDD) mode of UTRA.
Keywords :
3G mobile communication; FIR filters; field programmable gate arrays; reconfigurable architectures; FIR; FPGA; TDD mode; UMTS; Xilinx Virtex II Pro implementation; bit energy to interference ratio; digital channel filter; digital root raised cosine filter; field programmable gate array; filter length; finite impulse response; in-band signal powers; out-of-band signal powers; signal monitoring; terrestrial radio access mobile terminal receiver; time division duplex mode; universal mobile telecommunication system; 3G mobile communication; Batteries; Costs; Digital filters; Downlink; Field programmable gate arrays; Finite impulse response filter; Frequency; Interference; Switches;
Conference_Titel :
Electronic Design, Test and Applications, Proceedings. DELTA 2004. Second IEEE International Workshop on
Conference_Location :
Perth, WA, Australia
Print_ISBN :
0-7695-2081-2
DOI :
10.1109/DELTA.2004.10058
