High quality TPG for delay faults in look-up tables of FPGAs

The objective of this paper is to improve delay fault testing of SRAM-Based FPGAs. We have analyzed the physical behavior of resistive opens in a Look-Up Table (LUT) in previous papers and we have shown that i) these ones can change the propagation delay of the LUT and ii) the delay due to them varies depending on their size and their location. In this paper, we first show that resistive shorts are susceptible to make delay faults on the LUT output, leading to the same conclusions. As a result, we next show that the two-pattern pair and the implemented function of the LUT can significantly modify the sensitization of these defects, until making them non-observable on output. As a consequence, the basic properties for generating test vectors are not sufficient and new conditions are required to guarantee a most efficient delay test in a Manufactured-Oriented Test (MOT) context and in an Application-Oriented Test (AOT) context as well.