DocumentCode :
2840970
Title :
Versatile processor design for efficiency and high performance
Author :
Ziavras, Sotirios G.
Author_Institution :
Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
fYear :
2000
fDate :
2000
Firstpage :
266
Lastpage :
271
Abstract :
New architectural concepts are introduced for uniprocessor designs that conform to the data-driven computation paradigm. Usage of our D2-CPU (Data-Driven processor) follows the natural flow of programs, minimizes the number of redundant operations, lowers the hardware cost, and reduces the power consumption. Instructions enter the processing unit when they are ready to execute or when all their operand(s) are to be available within a few clock cycles. This approach results in outstanding performance and elimination of large numbers of redundant operations that plague current processor designs. A comparative analysis of our design with conventional designs proves that it is capable of better performance and higher efficiency
Keywords :
computer architecture; data flow computing; D2-CPU; architectural concepts; data flow computing; data-driven computation; performance; Bandwidth; Central Processing Unit; Computer aided instruction; Hardware; Multithreading; Out of order; Pipelines; Process design; Silicon; Yarn;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Architectures, Algorithms and Networks, 2000. I-SPAN 2000. Proceedings. International Symposium on
Conference_Location :
Dallas, TX
ISSN :
1087-4089
Print_ISBN :
0-7695-0936-3
Type :
conf
DOI :
10.1109/ISPAN.2000.900295
Filename :
900295
Link To Document :
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