Title :
Advanced platform-level clock jitter and drift analysis
Author_Institution :
Data Center Group, Intel Corp., Santa Clara, CA, USA
Abstract :
Platform clock plays a critical role for digital systems with high-speed serial links. Platform-level reference clock performance analysis is required for all system reference clock architectures to support different platform configurations. The paper presents the advanced platform-level clock jitter and drift methodology being often used by system engineers to guarantee the integrity of platform designs. The best known methods of platform-level clock jitter analysis from the clock sources to receivers due to different jitter characteristics in different clock distribution branches are presented. The novel platform-level cascaded PLL analysis for drift calculation and drift budgeting methodology are introduced.
Keywords :
clocks; phase locked loops; timing jitter; clock distribution; clock sources; digital systems; drift analysis; drift budgeting; high-speed serial links; platform clock; platform-level cascaded PLL analysis; platform-level clock jitter; reference clock; Clocks; Jitter; Noise measurement; Phase locked loops; Phase measurement; Phase noise; Transfer functions; FIFO; PLL; Q-scale; Reference clock; SSC; deterministic jitter; differential jitter; drift; filtered phase jitter; random jitter;
Conference_Titel :
Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2011 6th International
Conference_Location :
Taipei
Print_ISBN :
978-1-4577-1387-3
Electronic_ISBN :
2150-5934
DOI :
10.1109/IMPACT.2011.6117157
