• DocumentCode
    2841358
  • Title

    Advanced high density interconnection substrate for mobile platform application

  • Author

    Romero, Christian ; Park, Seungwook ; Kweon, Youngdo ; Park, Mijin

  • Author_Institution
    Corp. R&D Inst., Samsung Electromech. Co. Ltd., Suwon, South Korea
  • fYear
    2011
  • fDate
    19-21 Oct. 2011
  • Firstpage
    214
  • Lastpage
    217
  • Abstract
    The faster market trend towards smart phones with more advanced computing ability and connectivity will drive the greater need to incorporate more functionality in smaller space by integrating more components and functional blocks into convergent systems in form of chip-level (SOC) or die-level (SIP) packaging. As feature size continues to shrink, it requires combination of stringent design requirements which all interact in order to achieve the desired performance. Also, various limitations will arise in the design of the PCB in terms of size and signal integrity. The substrate or PCB plays critical role in the miniaturization of the overall system and the final application´s electrical performance. Given the extreme routing requirement of each component package with high I/O pins and fine pitch area array, the conventional HDI substrate pose some design challenges and limitations. In order to increase the routing density, it often requires smaller trace width and micro via diameter and even the need of adding more metal layers. These, however, will dramatically increase the cost and more reliability risk is expected. In this paper, we present a new generation substrate that could meet the mobile platform requirement by proposing an advanced ultra fine metal resolution substrate. It will demonstrate its high density interconnect capability in a basic 4-layer stack-up structure. One of its advanced features is the ability to adjust board and interconnection impedance in order to optimize signal integrity and more routing capability for dense mobile platform layouts. It will also demonstrate that organic-based substrate may also achieve tighter routing density using limited number of metal layers at smaller and thinner form factor while maintaining the desired signal integrity performance as compared to conventional 8-layer or 10-layer HDI PCBs. Details of electrical simulation and measurement of electrical parameters are also presented and discussed.
  • Keywords
    chip scale packaging; fine-pitch technology; integrated circuit interconnections; integrated circuit reliability; printed circuits; smart phones; system-in-package; system-on-chip; 4-layer stack-up structure; HDI PCB; I/O pins; SIP packaging; SOC packaging; chip-level packaging; dense mobile platform layouts; die-level packaging; fine pitch area array; high density interconnection substrate; microvia diameter; reliability; routing capability; signal integrity; smart phones; ultra fine metal resolution substrate; Impedance; Layout; Metals; Packaging; Radio frequency; Routing; Substrates;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2011 6th International
  • Conference_Location
    Taipei
  • ISSN
    2150-5934
  • Print_ISBN
    978-1-4577-1387-3
  • Electronic_ISBN
    2150-5934
  • Type

    conf

  • DOI
    10.1109/IMPACT.2011.6117163
  • Filename
    6117163