Title :
A LAYOUT DRIVEN DESIGN FOR TESTABILITY TECHNIQUE FOR MOS VLSI CIRCUITS
Author :
Kim, Sungho ; Banerjee, Prithviraj ; Patil, Srinivas
Keywords :
Circuit faults; Circuit testing; Costs; Degradation; Design for testability; Design methodology; Flip-flops; Sequential analysis; Sequential circuits; Very large scale integration;
Conference_Titel :
Test Conference, 1991, Proceedings., International
Print_ISBN :
0-8186-9156-5
DOI :
10.1109/TEST.1991.519506
