DocumentCode
2841445
Title
A LAYOUT DRIVEN DESIGN FOR TESTABILITY TECHNIQUE FOR MOS VLSI CIRCUITS
Author
Kim, Sungho ; Banerjee, Prithviraj ; Patil, Srinivas
fYear
1991
fDate
26-30 Oct 1991
Firstpage
157
Keywords
Circuit faults; Circuit testing; Costs; Degradation; Design for testability; Design methodology; Flip-flops; Sequential analysis; Sequential circuits; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1991, Proceedings., International
ISSN
1089-3539
Print_ISBN
0-8186-9156-5
Type
conf
DOI
10.1109/TEST.1991.519506
Filename
519506
Link To Document