On configuring scan trees to reduce scan shifts based on a circuit structure

In this paper, a new method for reducing test application time of sequential circuits with scan design is proposed. Scan design is one of most popular design for testability techniques. To reduce scan shifts required to provide the scan pattern, a fully testable scan tree configuration is proposed. The method can configure scan trees before generating test vectors without degrading fault coverage by considering a circuit structure. In a fully testable scan tree, flip-flops are placed in parallel in case that they have no overlap in the set of the outputs connected from them. To reduce much scan shifts, a folding scan tree, which is configured based on a fully testable scan tree by placing more flip-flops in parallel, is also configured. Moreover, a scan tree configuration considering scan-out operation is also presented. Experimental results for benchmark circuits are shown.