Scan test of IP cores in an ATE environment

Manufacturing test of chips made of multiple IP cores requires different techniques if ATE is used. As scan chains are commonly used as access paths to the DUT, ATE architectures must be designed to facilitate this arrangement. An increase in ATE performance for scan test requires a reduction in both scan time and memory utilization as commonly used figures of merit; in this paper, an ATE hardware architecture that allows the scan test to be done in an "interleaved" mode (thus separating the Scan-In and Scan-Compare sequences), is utilized together with a novel test scheduling algorithm. Two variations of the algorithm which permit test reordering and merging as well as an efficient generation of the so-called monolithic test sequence are proposed. Scheduling is found in polynomial time complexity and the proposed approach resorts to heuristic conditions for merging the vectors. A substantial saving in both test time and memory is achieved.