DocumentCode
2841603
Title
Design of routing-constrained low power scan chains
Author
Bonhomme, Y. ; Girard, P. ; Guiller, L. ; Landrault, C. ; Pravossoudovitch, S. ; Virazel, A.
Author_Institution
Lab. d´Inf. de Robotique et de Microelectron. de Montpellier, Univ. de Montpellier II, France
fYear
2004
fDate
28-30 Jan. 2004
Firstpage
287
Lastpage
292
Abstract
Scan-based architectures, though widely used in modern designs, are expensive in power consumption. Recently, we proposed a technique based on clustering and reordering of scan cells that allows to design low power scan chains. The main feature of this technique is that power consumption during scan testing is minimized while constraints on scan routing are satisfied. In this paper, we propose a new version of this technique. The clustering process has been modified to allow a better distribution of scan cells in each cluster and hence lead to more important power reductions. Results are provided at the end of the paper to highlight this point and show that scan design constraints (length of scan connections, congestion problems) are still satisfied.
Keywords
design for testability; integrated circuit design; integrated circuit testing; low-power electronics; network routing; clustering; integrated circuit testing; low power electronics; low power scan chains design; power consumption; scan based architectures; scan cells reordering; scan design constraints; scan routing; Circuit testing; Degradation; Design for testability; Electronic equipment testing; Energy consumption; Integrated circuit testing; Robots; Routing; System testing; Uniform resource locators;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Design, Test and Applications, Proceedings. DELTA 2004. Second IEEE International Workshop on
Conference_Location
Perth, WA, Australia
Print_ISBN
0-7695-2081-2
Type
conf
DOI
10.1109/DELTA.2004.10009
Filename
1409854
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