DocumentCode :
2841740
Title :
Filling TSV of different dimension using galvanic copper deposition
Author :
Rohde, Dirk ; Jager, Claus ; Hazin, Khatera ; Uhlig, Albrecht
Author_Institution :
Atotech Deutschland GmbH, Berlin, Germany
fYear :
2011
fDate :
19-21 Oct. 2011
Firstpage :
355
Lastpage :
358
Abstract :
Filling through silicon via (TSV) with copper is one important process step in 3D-integration. Void free and reliable galvanic copper deposition is essential for yield and lifetime of microelectronic devices. Different TSV applications, as chip stacking and interposer, require different TSV dimensions. This demands high flexibility and applicability for small and large via sizes in the galvanic filling process. This paper compares two different acidic copper systems in respect of their TSV filling properties. Both systems mainly differ in the leveler compound. System A shows super-conformal filling behavior and System B bottom-up filling. The properties of copper being deposited using System A and B respectively vary further in respect of copper grain size homogeneity, stress of the copper deposits, recrystallization temperature and incorporation of additives. The influence of organic copper additives on the mechanical, thermal, and electrical properties of the copper deposits is discussed. Using the example of System B, filling aspects as well as process optimization will be outlined. For process optimization electrochemical potential characteristics (E vs. t) during the filling process are used to identify important filling steps. Filling examples for small as well as large TSV feature sizes will be discussed.
Keywords :
additives; copper; electrochemistry; galvanising; integrated circuit yield; recrystallisation; three-dimensional integrated circuits; 3D-integration; acidic copper system; additive incorporation; bottom-up filling; chip stacking; copper deposit stress; copper grain size homogeneity; electrical property; electrochemical potential characteristics; filling through silicon via; galvanic copper deposition; galvanic filling process; interposer; mechanical property; microelectronic device lifetime; microelectronic device yield; organic copper additive; process optimization; recrystallization temperature; super-conformal filling behavior; thermal property; Additives; Copper; Current density; Filling; Stress; System-on-a-chip; Through-silicon vias;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2011 6th International
Conference_Location :
Taipei
ISSN :
2150-5934
Print_ISBN :
978-1-4577-1387-3
Electronic_ISBN :
2150-5934
Type :
conf
DOI :
10.1109/IMPACT.2011.6117182
Filename :
6117182
Link To Document :
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