A FPGA based driver drowsiness detecting system

A large number of traffic accidents are caused by the driver fatigue or drowsiness. These misfortunes can be avoided by keeping a close watch on tired characters of the driver and making a warning signal immediately. This function is implemented by a FPGA based vehicle driver surveillance system presented in this paper. Several well-known image processing algorithms like gray scale projection, edge detection with Prewitt operator and complexity function are combined together to judge whether the driver has his eyes closed. Their hardware architectures have been modeled using the Altera DSPBuilder and integrated as a co-processor to the main Nios II processor which controls the whole system. All of the algorithm hardware implementations have been achieved in a parallel and pipelined way and discussed in detail. The final system is based on the Altera Stratix II EP2S60 FPGA devices and has been proved to meet the basic requirements of drowsiness detection.