All digital phase interpolator

Author

Tsimpos, Andreas ; Souliotis, George ; Demartinos, Andreas ; Vlassis, Spiros

Author_Institution

Dept. of Phys., Univ. of Patras, Patras, Greece

fYear

2015

fDate

21-23 April 2015

Firstpage

1

Lastpage

6

Abstract

This paper proposes an all digital CMOS phase interpolator suitable for high-speed multi-Gigabit serial interfaces. The topology is based on the parallel combination of identical CMOS inverters grouped in eight segments and delivers two programmable orthogonal output phases (I/Q). The phase interpolator is designed to be compliant with MIPI alliance M-PHY standard in a 65nm CMOS process. Simulation results confirm 5-bit phase resolution with less than 5% worst case phase step variation, settling time less than 2 clock cycles and power consumption about 2mW from 1.2V voltage supply.

Keywords

CMOS digital integrated circuits; interpolation; logic gates; CMOS inverter; MIPI alliance MPHY standard; all digital phase interpolator; clock cycle; complementary metal oxide semiconductor; multigigabit serial interface; phase resolution; phase step variation; power consumption; programmable orthogonal output phase; size 65 nm; word length 5 bit; CMOS integrated circuits; Capacitors; Clocks; Gears; Interpolation; Inverters; Power demand; CMOS mixed mode circuits; Clock/data recovery circuits; High-speed integrated circuits; phase interpolators; receivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2015 10th International Conference on

Conference_Location

Naples

Type

conf

DOI

10.1109/DTIS.2015.7127354

Filename

7127354