All digital phase interpolator

This paper proposes an all digital CMOS phase interpolator suitable for high-speed multi-Gigabit serial interfaces. The topology is based on the parallel combination of identical CMOS inverters grouped in eight segments and delivers two programmable orthogonal output phases (I/Q). The phase interpolator is designed to be compliant with MIPI alliance M-PHY standard in a 65nm CMOS process. Simulation results confirm 5-bit phase resolution with less than 5% worst case phase step variation, settling time less than 2 clock cycles and power consumption about 2mW from 1.2V voltage supply.