Rapid solution of the finite difference time domain method using parallel associative techniques

The authors describe a method for mapping FDTD onto a new parallel architecture, the associative string processor (ASP). This architecture is particularly suited to FDTD since it avoids the communications bottleneck which other parallel implementations of FDTD have encountered. The mapping technique presented is not problem-dependent and has an enormous speed advantage. This gives rise to the possibility of incorporating FDTD into a integrated circuit and layout simulation tool and allows far more complex problems to be analysed within realistic processing times. The mapping is described in detail and then equations are derived for the processing time required for each part of the algorithm. A general method for predicting the time taken for a given problem is obtained from these equations. The particular case of a microchip low-pass filter is used to illustrate the size of the improvements possible with the new mapping when compared with a conventional computer architecture