Application-independent testing of multilevel interconnect in mesh-based FPGAs

Author

Rehman, Saif Ur ; Benabdenbi, Mounir ; Anghel, Lorena

Author_Institution

TIMA Lab., Grenoble-Alpes Univ., Grenoble, France

fYear

2015

fDate

21-23 April 2015

Firstpage

1

Lastpage

6

Abstract

This paper presents a BIST scheme for a new hierarchical interconnect topology in mesh FPGAs. The proposed technique ensures full test and diagnosis by performing selection of test paths. It uses 2×2 adjacent logic resources. Using this scheme, any N×N FPGA array can be further tested by N parallel 2×2 array procedure which ultimately reduces the test time. The efficiency of this scheme is evaluated in terms of the number of configurations required for a complete testing of global interconnect in cluster-based FPGAs for different cluster sizes. Automated tools are developed to generate the test configuration bitstreams and to integrate them into a standard FPGA CAD flow. Simulation results show that 100% test coverage for stuck-at and pair-wise bridging faults can be achieved with high diagnostic resolution.

Keywords

built-in self test; field programmable gate arrays; integrated circuit interconnections; logic testing; BIST scheme; FPGA array; adjacent logic resources; application-independent testing; automated tool; cluster-based FPGA; global interconnect testing; hierarchical interconnect topology; mesh-based FPGA; multilevel interconnect; pair-wise bridging faults; standard FPGA CAD flow; stuck-at faults; test configuration bitstreams; test path selection; Built-in self-test; Fault detection; Field programmable gate arrays; Multiplexing; Topology; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2015 10th International Conference on

Conference_Location

Naples

Type

conf

DOI

10.1109/DTIS.2015.7127383

Filename

7127383