DocumentCode
2842677
Title
Reducing the power consumption of FPGAs through retiming
Author
Fischer, Robert ; Buchenrieder, Klaus ; Nageldinger, Ulrich
Author_Institution
Inst. for Comput. Eng., Univ. der Bundeswehr, Munich, Germany
fYear
2005
fDate
4-7 April 2005
Firstpage
89
Lastpage
94
Abstract
High power dissipation is one of the major disadvantages of FPGAs. A main part of the power consumed is caused by glitches. This paper analyzes the effect of retiming to reduce the power dissipation of a Xilinx Virtex-II FPGA. The authors introduce a method to insert staging registers into large designs, that are constructed from a high abstraction level language algorithmic description. Results obtained by measurements suggest a high potential for power savings through retiming.
Keywords
field programmable gate arrays; logic CAD; power consumption; timing; FPGA; Xilinx Virtex-II FPGA; power consumption; power dissipation; power saving; Application specific integrated circuits; Delay; Energy consumption; Field programmable gate arrays; Power dissipation; Power engineering and energy; Power engineering computing; Production; Signal processing algorithms; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Engineering of Computer-Based Systems, 2005. ECBS '05. 12th IEEE International Conference and Workshops on the
Print_ISBN
0-7695-2308-0
Type
conf
DOI
10.1109/ECBS.2005.58
Filename
1409905
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