Title :
The solder joint reliability assessment of a wafer level CSP package
Author :
Chung, Kuan-Jung ; Tseng, Chih-Hao ; Yang, LiYu
Author_Institution :
Dept. of Mechatron. Eng, Nat. Changhua Univ. of Educ., Changhua, Taiwan
Abstract :
A WLCSP package consists of 2.2 × 2.2 mm2 silicon die, polyimide-based substrate, and 5 × 5 array of solder balls was used as the test vehicle to evaluate its solder joint reliability. Both package level tests with respect to precondition test, temperature cycling test, unbiased highly accelerated stress test (UHAST), and high temperature storage life (HTSL) test and board level tests regarding temperature cycling test have been included in the test plan. Two different lead free solder ball materials (SAC1205 vs. SAC105), under bump metallurgy (Ti/NiV/Cu vs. plated Cu), and die thicknesses (406 μm vs. 356 μm) were assessed. The test results for the package level assessment present that the test vehicle past criteria for all of these required tests. The test results of temperature cycling (-40°C ~125°C) for the board level assessment show that these controlled variables have unlike performance in the solder joint reliability (SJR) of the WL-CSP package. The SAC105 shows better solder joint reliability performance than that of SAC1205 to provide 13 % improvement in characteristic life (Weibull distribution). The thick die (406 μm) shows statistically better SJR performance than that of thin die (356 μm) to sustain 10% increase in characteristic life (Weibull distribution). On the other hand, standard Ti/NiV/Cu UBM presents statistically equivalent SJR performance as plated Cu in characteristic life. As the results, package design factors of the solder alloy and die thickness play obvious roles in solder joint reliability compared to the factor of UBM. Generally speaking, the WL-CSP package presents appropriate solder joint reliability according to the test results.
Keywords :
integrated circuit reliability; solders; wafer level packaging; HTSL test; UHAST; WLCSP package; board level tests; high temperature storage life test; package level tests; polyimide-based substrate; precondition test; silicon die; size 356 mum; size 406 mum; solder ball materials; solder joint reliability assessment; temperature cycling test; unbiased highly accelerated stress test; wafer level CSP package; Copper; Dielectrics; Semiconductor device reliability; Soldering; Vehicles;
Conference_Titel :
Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2011 6th International
Conference_Location :
Taipei
Print_ISBN :
978-1-4577-1387-3
Electronic_ISBN :
2150-5934
DOI :
10.1109/IMPACT.2011.6117252