Title :
A parallel multilevel low-rank decomposition algorithm for fast simulation of high-speed electronic interconnect and packages
Author :
Yang, Chuanyi ; Chakraborty, Swagato ; Gope, Dipanjan ; Ouyang, Gong ; Jandhyala, Vikram
Author_Institution :
Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
Abstract :
A high performance, parallel multilevel low-rank decomposition algorithm for fast integral equation based simulation of high-speed interconnect and packages was proposed. Good linear scalability was achieved through the included load-balancing scheme and minimized inter-process communication. The method shows promise in enabling large scale simulation at unprecedented scale.
Keywords :
integral equations; integrated circuit interconnections; integrated circuit packaging; fast integral equation; high-speed electronic interconnect; high-speed electronic packages; inter-process communication; large scale simulation; linear scalability; load-balancing scheme; low-rank decomposition algorithm; parallel multilevel algorithm; Boundary conditions; Data structures; Differential equations; Electronics packaging; High-speed electronics; Integral equations; Large-scale systems; Linear systems; Matrix decomposition; Scalability;
Conference_Titel :
Electrical Performance of Electronic Packaging, 2005. IEEE 14th Topical Meeting on
Print_ISBN :
0-7803-9220-5
DOI :
10.1109/EPEP.2005.1563749
