• DocumentCode
    2843199
  • Title

    Correlation between Shadow Moiré and Micro Moiré techniques through characterization of flip-chip BGA

  • Author

    Liu, An-Hong ; Wang, David W. ; Huang, Hsiang-Ming ; Sun, Ming ; Lin, Muh-Ren ; Zhong, Chonghua ; Hwang, Sheng-Jye ; Lu, Hsuan-Heng ; Bui, Huy-Tien ; Deng, Shang-Shiuan

  • Author_Institution
    ChipMos Technol. Inc., Tainan, Taiwan
  • fYear
    2011
  • fDate
    19-21 Oct. 2011
  • Firstpage
    269
  • Lastpage
    272
  • Abstract
    Although the reliability of chip-substrate interconnect joint has been well recognized by using leaded or lead-free solder bumps and Cu pillar, the relative displacement induced by package warpage between the bump and bump pad received significantly increasing interest, especially for those devices with low K materials and fine-pitch interconnects as the pitch becomes smaller and the package body size becomes larger in flip chip technology. In order to study the physical relationship between micron-level warpage of the package and nano-level displacement of the solder bumps, 1112-ball flip-chip BGA with and without a heat spreader was measured by using Shadow Moiré technique and Micro Moiré interferometry in this study. Shadow Moiré technique was used to characterize the overall warpage of the package between room temperature and solder ball reflow temperature of 230°C and Micro Moiré interferometry was used at room temperature and 114°C. From the results by Shadow Moiré, a heat spreader could alter the warpage pattern of the package from convex (w/o) to concave (w/o) and the amount of warpage was well-controlled under 16um. Furthermore, the correlations between Shadow Moiré and Micro Moiré were also described in this study. This study developed a useful approach and made direct estimations for the displacement of solder bumps to the possibility that could be contributive to the evaluation of the reliabilities of chip-level interconnects and packaging design.
  • Keywords
    ball grid arrays; flip-chip devices; integrated circuit interconnections; integrated circuit reliability; solders; Cu pillar; ball flip-chip BGA; bump pad; chip-level interconnect; chip-substrate interconnect joint; fine-pitch interconnects; flip chip technology; heat spreader; lead-free solder bump; micromoiré interferometry; micron-level warpage; nano-level displacement; package warpage; packaging design; reliability; shadow Moiré technique; solder ball reflow; solder bumps; temperature 114 C; temperature 230 C; warpage pattern; Heating; Interferometry; Semiconductor device measurement; Silicon; Substrates; Temperature measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2011 6th International
  • Conference_Location
    Taipei
  • ISSN
    2150-5934
  • Print_ISBN
    978-1-4577-1387-3
  • Electronic_ISBN
    2150-5934
  • Type

    conf

  • DOI
    10.1109/IMPACT.2011.6117261
  • Filename
    6117261