On chip circuit model for accurate mid-frequency simultaneous switching noise prediction

An on chip circuit model for accurate mid-frequency simultaneous switching noise (SSN) prediction has been studied in this paper. Voltage controlled switching resistors, voltage controlled leakage resistors have been proposed to represent the switching activities and leakage of a chip. Empirical formulas are presented for the calculations of resistors. The on chip power grid impacts on mid-frequency SSN as well as the clock frequency noise have been analyzed. For mid-frequency SSN prediction, we don´t have to include on chip power grid in the model except an accurate intrinsic capacitance extraction. However, for clock-frequency noise, we need the on chip power grid characteristics.