Title :
ACHIEVING COMPLETE DELAY FAULT TESTABILITY BY EXTRA INPUTS
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Keywords :
Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Delay; Design for testability; Hardware; Logic testing; Minimization; Robustness;
Conference_Titel :
Test Conference, 1991, Proceedings., International
Print_ISBN :
0-8186-9156-5
DOI :
10.1109/TEST.1991.519519
