Title :
A Methodology for Designing Optimal Self-Checking Sequential Circuits
Author :
Parekhji, R.A. ; Venkatesh, G. ; Sherlekar, S.D.
Keywords :
Circuit faults; Condition monitoring; Coprocessors; Cost function; Delay; Design methodology; Encoding; Sequential circuits; Testing;
Conference_Titel :
Test Conference, 1991, Proceedings., International
Print_ISBN :
0-8186-9156-5
DOI :
10.1109/TEST.1991.519520
