DocumentCode

2843885

Title

A Methodology for Designing Optimal Self-Checking Sequential Circuits

Author

Parekhji, R.A. ; Venkatesh, G. ; Sherlekar, S.D.

fYear

1991

fDate

26-30 Oct 1991

Firstpage

283

Keywords

Circuit faults; Condition monitoring; Coprocessors; Cost function; Delay; Design methodology; Encoding; Sequential circuits; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1991, Proceedings., International

ISSN

1089-3539

Print_ISBN

0-8186-9156-5

Type

conf

DOI

10.1109/TEST.1991.519520

Filename

519520