A Multiple-Bandwidth 10-bit SAR Analog to Digital Converter

Author

Adimulam, Mahesh Kumar ; Movva, Krishna Kumar ; Veeramachaneni, Sreehari ; Muthukrishnan, N. Moorthy ; Srinivas, M.B.

Author_Institution

Dept. of ECE, Birla Inst. of Technol. & Sci. - Pilani, Hyderabad, India

fYear

2011

fDate

19-21 Dec. 2011

Firstpage

24

Lastpage

29

Abstract

In this paper, a multi bandwidth 10-bit SAR analog to digital converter (ADC) with edge-combiner digital delay locked loop (DDLL) circuit for self clock generation is proposed. The ADC circuit in the proposed design avoids external clock signal for sampling and clock is generated from analog input signal for a wide range of frequency operation. The proposed ADC design is capable of operating over the input frequency range of 10Ksps to 1.8Msps with 40MHz maximum sampling clock. The proposed ADC have been designed and verified for post layout simulations in standard 65nm CMOS technology which has DNL <; ±0.1LSB, INL <; ±0.15LSB and SFDR of 61.38dB and maximum power consumption of 2mW @ 1.2V supply voltage at 10-bit with 40MHz sampling clock.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; delay lock loops; integrated circuit design; DDLL circuit; edge-combiner digital delay locked loop circuit; frequency 40 MHz; multibandwidth ADC circuit; multiple-bandwidth SAR analog-to-digital converter; post layout simulations; power 2 mW; sampling clock; self-clock generation; size 65 nm; standard CMOS technology; successive approximation register; voltage 1.2 V; Bandwidth; Clocks; Delay; Frequency control; Frequency conversion; Photonic band gap; Threshold voltage; Digital Delay Locked Loop [DDLL]; Latch Comparator and SAR ADC; Low Power; Oscillator;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic System Design (ISED), 2011 International Symposium on

Conference_Location

Kochi, Kerala

Print_ISBN

978-1-4577-1880-9

Type

conf

DOI

10.1109/ISED.2011.63

Filename

6117320