A Reconfigurable INC/DEC/2´s Complement/Priority Encoder Circuit with Improved Decision Block

Author

Kumar, V. Chetan ; Phaneendra, P. Sai ; Ahmed, Syed Ershad ; Sreehari, V. ; Muthukrishnan, N. Moorthy ; Srinivas, M.B.

Author_Institution

Dept. of Electr. Eng., Birla Inst. of Technol. & Sci.-Pilani, Hyderabad, India

fYear

2011

fDate

19-21 Dec. 2011

Firstpage

100

Lastpage

105

Abstract

An Increment/Decrement circuit is a common building block in many digital systems like address generation unit which are used in micro controllers and microprocessors. Similarly 2´s complement and priority encoder circuits are used in many applications. This paper presents an improvement to the decision block of the existing INC/DEC architectures. This improvement results in up to 48% reduced delay and 50% reduced power delay product. This paper also proposes a reconfigurable INC/DEC/2´s complement/Priority encoder circuit which uses the new proposed decision blocks.

Keywords

decision theory; encoding; microcontrollers; reconfigurable architectures; 2´s complement circuit; address generation unit; decision block; digital system; increment-decrement circuit; microcontroller; microprocessor; priority encoder circuit; reconfigurable INC-DEC circuit; Adders; Arrays; Complexity theory; Delay; Logic gates; Simulation; Zinc; 2´s compelment; Reconfigurable; increment/decrement; priority encoder;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic System Design (ISED), 2011 International Symposium on

Conference_Location

Kochi, Kerala

Print_ISBN

978-1-4577-1880-9

Type

conf

DOI

10.1109/ISED.2011.52

Filename

6117334